The present invention relates to a method of and all apparatus for logic circuit synthesis for automatically synthesizing a logic circuit according to a description of the logic circuit using a HDL (High-level Design Language) and a recording medium wherein a program for a computer performing the logic circuit synthesis according to the method is recorded.
As one of prior arts of the logic circuit synthesis, there is known a method disclosed in "BooleDozer: Logic synthesis for ASICs" by L. Stok et al., IBM J. RES. DEVELOP., VOL. 49, NO. 4, pp. 407-430 (July 1996).
FIG. 11 is a block diagram schematically illustrating a structural flow of the above prior art.
Referring to FIG. 11, the prior art apparatus comprises a compiler section 104, a technology-independent optimization section 105, a technology mapping section 106, a timing optimization section 107, a logic circuit output section 108, a semiconductor library 103 and an inner database 102 used by the above sections.
The compiler section 104 compiles a HDL description 101 into a logical network composed of logical blocks including equation blocks, functional blocks such as adders and multiplexers, and primitive gates. The logical network is stored in the inner database 102.
The technology-independent optimization section 105 performs technology-independent optimization of the logical network. Here, the technology-independent optimization means optimization not considering concrete hardware configurations of the logical blocks. In this prior art example, optimization methods such as so-called the constant propagation, the redundancy removal, the global flow analysis, the transduction, the cube factoring, and the kernel factoring are applied for the technology-independent optimization.
Then, referring to the semiconductor library 103, the technology mapping section 106 generates a hardware network by assigning a matching hardware unit to each of the logical blocks of the logical network after processed through the technology-independent optimization section 105. The hardware network is stored in the inner database 102.
The timing optimization section 107 performs optimization of the hardware network referring to the semiconductor library 103, making use of optimization methods such as so-called the fan-out correction, the fan-in reordering, the decomposition, and the inverter motion.
Finally, the logic circuit output section 108 generates a logic circuit 111 to be output referring to the semiconductor library 103 according to the hardware network after processed through the timing optimization section 107.
Thus, a logic circuit is synthesized according to a HDL description in the prior art example.
However, in the conventional logic circuit synthesis such as above described, there has been a problem that one-to-one correspondences are not all retained between the HDL description and the logic circuit synthesized according thereto. This is because part of the information in the HDL description disappears in the process of the optimization.
For example, following logic in the HDL description;
S=(A and C) or (A and D) or (B and C) or (B and D), PA1 P=(A and S), and PA1 Q=(B and S), PA1 S'=(C or D) PA1 P=(A and S'), and PA1 Q=(B and S'). PA1 compiling a HDL description into a logical network, wherein boundary information concerning intermediate signals defiled in the HDL description is included; PA1 performing technology-independent optimization of the logical network retaining the boundary information; PA1 transforming the logical network into a hardware network retaining the boundary information, by assigning a matching hardware unit in a semiconductor library to each of logical blocks of the logical network after performing the technology-independent optimization; PA1 performing optimization of the hardware network referring to the semiconductor library and retaining the boundary information, the optimization being performed concerning at least one of circuit size, operational speed and power consumption of a logic circuit to bc designed according to the hardware network; PA1 generating the logic circuit to be output referring to the semiconductor library according to the hardware network after performing the optimization; and PA1 outputting a correspondence list describing information of each respective point of the logic circuit corresponding to each of intermediate signals included in the boundary information, by editing the boundary information. PA1 generating a primitive logical network by simply transferring each of symbols and logical equations defined in the HDL description into equivalent each of simple nodes, links and logical blocks of the primitive logical network, each of symbols of the intermediate signal being transferred into a node accompanied by a signal name of corresponding each of the intermediate signals; PA1 extracting the boundary information from the primitive logical network by searching the primitive logical network for every node accompanied by a signal name; and PA1 erasing each node accompanied by a signal name in the primitive logical network, by attaching the boundary information including the signal name to a preceding node of the node and connecting every of following node of the node to the preceding node. PA1 performing constant propagation optimization of the logical network to be performed following the step of compiling, wherein the boundary information concerning intermediate signals found to be constant is allowed to be erased; and PA1 performing boundary information reduction by checking whether a fan-out number of a node is more or not than a predetermined number for every node of the logical network accompanied by the boundary information concerning any of the intermediate signals, and erasing the boundary information of nodes each giving the fan-out number not more than the predetermined number; PA1 a compiler section for compiling a HDL description into a logical network, wherein boundary information concerning intermediate signals defined in the HDL description is included; PA1 a technology-independent optimization section for performing technology-independent optimization of the logical network retaining the boundary information; PA1 a technology mapping section for transforming the logical network into a hardware network retaining the boundary information, by assigning a matching hardware unit in cl semiconductor library to each of logical blocks of the logical network after processed with the technology-independent optimization; PA1 a timing optimization section for performing optimization of the hardware network referring to the semiconductor library and retailing the boundary information, the optimization being performed concerning at least one of circuit size, operational speed and power consumption of a logic circuit to be designed according to the hardware network; PA1 a logic circuit output section for generating the logic circuit to be output referring to the semiconductor library according to the hardware network after processed with the optimization; and PA1 a correspondence list output section for outputting a correspondence list describing information of each respective point of the logic circuit corresponding to each of intermediate signals included in the boundary information, by editing the boundary information. PA1 a translator for generating a primitive logical network by simply transferring each of symbols and logical equations defined in the HDL description into equivalent each of simple nodes, links and logical blocks of the primitive logical network, each of symbols of the intermediate signal being transferred into a node accompanied by a signal name of corresponding each of the intermediate signals; and PA1 a boundary information generating section for extracting the boundary information from the primitive logical network by searching the primitive logical network for every node accompanied by a signal name, and erasing each node accompanied by a signal name in the primitive logical network, by attaching the boundary information including the signal name to a preceding node of the node and connecting every of following node of the node to the preceding node. PA1 a constant propagation section for performing constant propagation optimization of the logical network wherein the boundary information concerning intermediate signals found to be constant is allowed to be erased; and PA1 a reference number checking section for performing boundary information reduction by checking whether a fan-out number of a node is more or not than a predetermined number for every node of the logical network accompanied by the boundary information concerning alkyl of the intermediate signals, and erasing the boundary information of nodes each giving the fan-out number not more than the predetermined number; PA1 compiling a HDL description into a logical network, wherein boundary information concerning intermediate signals defined in the HDL description is included; PA1 performing technology-independent optimization of the logical network retaining the boundary information; PA1 transforming the logical network into a hardware network retaining the boundary information, by assigning a matching hardware unit in a semiconductor library to each of logical blocks of the logical network after performing the technology-independent optimization; PA1 performing optimization of the hardware network referring to the semiconductor library mid retaining the boundary information, the optimization being performed concerning at least one of circuit size, operational speed and power consumption of a logic circuit to be designed according to the hardware network; PA1 generating the logic circuit to be output referring to the semiconductor library according to the hardware network after performing the optimization; and PA1 outputting a correspondence list describing information of each respective point of the logic circuit corresponding to each of intermediate signals included in the boundary information, by editing the boundary information. PA1 generating a primitive logical network by simply transferring each of symbols and logical equations defined in the HDL description into equivalent each of simple nodes, links and logical blocks of the primitive logical network, each of symbols of the intermediate signal being transferred into a node accompanied by a signal name of corresponding each of the intermediate signals; PA1 extracting the boundary information from the primitive logical network by searching the primitive logical network for every node accompanied by a signal name; and PA1 erasing each node accompanied by a signal name in the primitive logical network, by attaching the boundary information including the signal name to a preceding node of the node and connecting every of following node of the node to the preceding node. PA1 performing constant propagation optimization of the logical network to be performed following the step of compiling, wherein the boundary information concerning intermediate signals found to be constant is allowed to be erased; and PA1 performing boundary information reduction by checking whether a fail-out number of a node is more or not than a predetermined number for every node of the logical network accompanied by the boundary information concerning any of the intermediate signals, and erasing the boundary information of nodes each giving the fan-out number not more than the predetermined number.
is transformed, as the result of optimization according to the transduction, into another logic as follows;
Thus, all intermediate signal S=(A and C) or (A and D) or (B and C) or (B and D) defined in the HDL description 101 is replaced with different intermediate signal S'=(C or D) in the synthesized logic circuit 111, according to the prior art logic circuit synthesis. Here, the intermediate signal means a signal other than input/output signals of a logic circuit itself designed with a HDL module or output signals of sequential hardware units such as a flip-flop in the logic circuit. Similar omissions or deformations occur through the other optimization methods than the transduction.
When a logic circuit is sufficient to be once synthesized simply, the correspondence between the logic circuit and the HDL description may not be necessary to be referred to.
However, in most cases, the synthesized logic circuit should be checked as to whether it functions correctly as intended by the designer making use of detailed simulation, for example, even if the logic circuit is correctly synthesized according to a HDL description. This is because the logic circuit synthesis cannot check for a the desiginer's intention itself even if it can check logical inconsistency in the HDL description. Further, the designer may intend to revise the HDL description for improving performance of the synthesized logic circuit concerning a critical path thereof.
In these cases, it is difficult for the designer to correctly search corresponding parts of the HDL description when information of the intermediate signals is omitted or deformed automatically through the optimization.
When no optimization is applied, the above problem does not occur, of course, but performance (in area, delay and power) of the synthesized logic circuit would be too degraded.